5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证，一、具有很高的速率,5-order CIC filter, collected 12 times the Verilog procedures are by simulation, one with a very high rate

这是关于fallow滤波器的设计，设计平台为FPGA，使用verilog语言，希望对使用者能用帮助-This is the fallow filter design, design platform FPGA, using verilog language, and I hope to be able to help users

数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program