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Verilog数字系统设计教程(第2版)
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed o
bb.rar
- 乒乓结构的verilog程序，风格相当好。大家赶紧 下了啊。,Verilog procedural ping-pong structure, style pretty good. Under the U.S. quickly, ah.
synchronisation
- This circuit is a nice edge detector that gives you synchronous notification of edges on your input signal. There s no excuse for not doing this it s a tiny circuit in just five lines of Verilog.-This circuit is a nice edge detector that gives yo
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
8_oeder_signed_parellel_DA_FIR
- 本程序使用Verilog编写的程序。 本例是1个8阶对称系数的FIR滤波器，采用并行分布式算法。输入位宽为12位，输入是有符号的，即有正有负。-it s a program with Verilog
bluespec-reedsolomon_latest.tar
- Reed Solomon decoder implemented in VHDL/Verilog. Includes ASM s
fft
- altera公司fft ip核的运用。语言是verilog.-Altera company s fft ip. Language verilog.
RTL_Compiler_synthesis.pdf
- HOW TO SYNTHESIZE VERILOG CODE USING RTL COMPILER This tutorial explains how to synthesize a verilog code using RTL Compiler. In order to do so, let’s consider the verilog codes below.
TTLV-Nguyen-Vu-Quang
- THIS document was written by verilog code. It s content talkes about descr iption 64 FFT
AES
- It s AES codes which is written by verilog.
AES_astro
- It s AES_astro codes which is written by verilog.
LED_KEY
- MAX10的led小程序，用Verilog语言写的。分享下，请收下-The code is about MAX10 s led.Share about people.