verilog 写的工程，是个基于流水线的乘法器-verilog write the works, is based on a pipelined multiplier

cordic的fpga实现，基于verilog硬件语言实现，实现高速流水线的CORDIC。-cordic fpga implementation, hardware-based verilog language, to achieve high-speed pipelined CORDIC.