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dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码,在ModelSim中仿真通过,并且在ISE中能综合!即可以下载到FPGA中运行指令,指令可以根据需要定义,也可和相应的编译器配合使用,这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
cpu
- vhdl编的cpu,自己的课程验收实验,微指令实现,流程详细。存储,加减基本运算均有,乘法使用位移相加法得到。其中excel有微程序控制信号的编码,储存ram编写,控制器rom编写等-vhdl code of cpu, its acceptance test program, microcode implementation process in detail. Storage, addition and subtraction are the basic operations, multipl
VHDL
- 将音乐数据存储到LPM-ROM,就达到了以纯硬件的手段来实现乐曲的演奏效果。只要修改LPM-ROM所存储的音乐数据,将其换成其他乐曲的音乐数据,再重新定制LPM-ROM,连接到程序中就可以实现其它乐曲的演奏。-oring music data to LPM-ROM, reached with pure hardware means to achieve the effect of music playing. Just modify LPM-ROM music stored data, whic