Altera NIOS II SPI 驱动-Altera NIOS II uart DRIVER

主控芯片altera的ep3c,由spi模块接受外部数据，经由计算控ad9910，参考频率由adf4360产生。-The the the master chip altera ep3c, spi module accepts external data through the calculation control ad9910, reference frequency generated by adf4360.

SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE

ad9628配置，给出了spi配置接口的时序描述。设计中需要例化altera的fifo。(ad9628 configure with spi configuration timing,and there is a QuartusII fifo in the design.)