OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证-OVL- assertion-based verification of Verilog Verilog digital system design: RTL synthesis, test and verification platform

利用SPI实现FPGA和外设之间的通信。经过Modelsim仿真验证。（为FPGA设计技巧与案例开发详解一书源码）(Using SPI to implement communication between FPGA and peripheral. After Modelsim simulation verification. (for FPGA design techniques and case development detailed explanation of a book source