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div_3
- verilog 三分频器 并含仿真文件 波形-Verilog three dividers and documents containing waveform simulation
fre_division
- 使用verilog编写分频器，包括奇分频和偶分频，可以进行任意奇偶分频
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
frequence_20
- 20分频器，具有一定的使用价值，自己可以试试看 。-20 frequence verilog code design and test
div5
- 用verilog描述的任意分频器，包括奇偶分频。-Any divider verilog descr iption, including the parity divide.
half_clk
- 此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha