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256点FFT源代码
- 256点FFT IP核。包括16bit和8bit两种精度和C、VHDL、Verilog三种语言的多版本、多精度的IP核
512点FFT
- 512点FFT IP核。包括C、VHDL和Verilog三种语言版本,8bit与16bit两种精度。
Verilog数字系统设计教程(第2版)
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案,要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed o
MIP-C
- mips-c指令系统,用Verilog实现-mips-c command systems, using Verilog realization of
MIPSCPU
- 用verilog描述一个mips体系结构的cpu,分别用c语言mips汇编语言写了一段程序,翻译成机器码可以再cpu上运行。仿真结果三者完全一致。-Mips architecture cpu with verilog descr iption c language mips assembly language to write a program, translated into machine code can then cpu running on. Simulation results e
c
- 通过verilog HL语言实现自动加减法功能-By verilog HL language for automatic subtraction function
code_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码,输入信号有时钟、时钟使能、复位、给定的卫星编号,输出产生的C/A码。此程序在代码上进行优化,占用了更少的资源。--This program generates Verilog GPS satellite navigation signals for C/A code, the input signal with a clock, clock enable, reset, given the satellite number, the ou