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SPI-PRT
- 昨天在论坛上看到有人帖出了他写的并串转换VHDL代码，但是他自己说有问题，但是不知道怎么改。我大概看了一下，发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably wat
jicifenpinqi
- 别人编写的奇次分频器，用VHDL写的，我已经在QUARTUS上验证过了-others prepared by the odd dividers, VHDL write, I have QUARTUS tested the
AD7864
- 这是对上次AD7864采样程序的改进，增加了FIFO的编程，功能比上次源码更加完善！-This sourse is modified and I have added the program of FIFO,so its function is better then privious one.I hope it is helpful for you!
second
- 上传个EDA得VHDL语言编程得秒计时器，希望对大家能有所帮助 谢谢了-From months EDA was VHDL language programming a second timer, I hope all of you can help I would like to thank the
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶
vhdl.tar
- vdhl and matlab, i think it good for you
processor.tar
- i need of vhdl code for 32-bit risc processor
uart
- i like verilog VHDL and system Verilog
lcdtest2
- 很不错的VHDL；是啊啊；我觉得这个文件关于LCD的显示有所帮助；-Very good VHDL yes ah ah I think this help file on the LCD display
PerceptronModel
- Actually the file paltform is verilog, But I can t find the verilog in the platform list. So I choose the VHDL.
eetop.cn_sdram_mdl
- 分类中没有verilog，其实代码是verilog写的，大家下载的时候注意一下哈-There is no Verilog subcatalog in the list,so I choose the VHDL.Please pay attention to this when download it.
bin_count
- i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.