VHDL实现fpga的信号ADC采集，适合zybo，zedboard等板子-VHDL realization fpga signal ADC acquisition for zybo, zedboard and other board

基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve

C语言，模拟交通灯信号。基于FPGA，需要连接至屏幕使用，可以运行。(FPGA traffic light, c language)