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clock
- 用vhdl开发的up3 clock,可以在up3的led上显示24小时制时分秒
1234
- 多功能数字钟，、在quartus 2环境中编译通过； 4、仿真通过并得到正确的波形； 5、给出相应的设计报告 -Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
clock
- EDA 数字钟实现文件 能够实现计时,闹钟,校时功能 -EDA digital clock time to achieve the realization of paper, alarm clock, school functions
clock
- 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
workhard
- 数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能-Digital clock can be calibrated to achieve a normal count timekeeping function of the radio side there are four low and one high alarm
clock
- 完成数字钟表的功能，可以实现整点报时，闹钟和设置时间-The completion of the functions of digital watches, you can bring the whole point timekeeping, alarm clock and set-up times
digital_clk
- 此程序是实现数字钟的，包括校时 闹钟 二十四小时和十二小时的转换-This procedure is to achieve digital clock, including the school alarm clock 24 hours and 12 hours the conversion
clock
- 电子课程设计数字钟的源代码，已在试验箱上实现，定义了管脚。可以调整时间-E-curriculum design digital clock source code has been achieved in the chamber, the definition of a pin. Can adjust the time
clock
- 数字钟是采用数字电路实现“时”、“分”、“秒”数字显示的计时装置。由于数字集成电路的发展和石英晶体震荡器的使用，使得数字钟的精度、稳定度远远超过了机械钟表，已成为人们日常生活中必不可少的必需品。-Digital Clock is a digital circuit implementation, " when" , " sub" , " second" The figures show that the timing device. Digita
EDAtest
- 关于数字钟的实现，用VHDL实现时，分，秒，的显示，并能报时-Digital clock on the realization of VHDL to achieve with hour, minute, seconds display, and time
shuzhizhong(vhdl)
- 数字钟设计 计时计数器用24进制计时电路； 可手动校时，能分别进行时、分的校正； 整点报时； 选做：可设置闹时功能，当计时计到预定时间时，扬声器发出闹铃信号，闹铃时间为4s，并可提前终止闹铃。-Digital clock design
lcd12864
- fpga驱动lcd12864显示时钟，vhdl语言描述-the fpga drive lcd12864 display clock
UART_RS232(VHDL)
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状
sy
- 利用VHDL语言设计的电子数字钟，有时、分钟、秒钟计数器、还有整点报时报警。-Design using VHDL language electronic digital clock, sometimes, minutes, seconds counter, as well as the whole point timekeeping alarm.
counter_
- VHDL源代码+工程，可改变时钟的计数器-VHDL source code+ project, can change the clock counter
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
VHDL
- 里面有微机的（关于数据字符的存储）、EDA、还有时钟电路的一些代码-Some code inside the computer (for the character data storage), EDA, as well as the clock circuit
EDA
- EDA实验程序：60进制，数字钟 ，表决器 包括VHDL语言和图的连线-EDA experimental procedure: 60 binary, digital clock, voting Including connection VHDL language and graphs