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async_transmitter
- 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
async_receiver
- 用verilog实现rs232 receiveri -with verilog achieve rs232 receiveri
verilog
- verilog设计经验点滴 因为Verilog是一种硬件描述语言，所以在写Verilog语言时，首先要有所要写的module在硬件上如何实现的概念，而不是去想编译器如何去解释这个module-verilog technolog
MIP-C
- mips-c指令系统,用Verilog实现-mips-c command systems, using Verilog realization of
shiyan6
- 使用Verilog实现十分进和六进制，并组合成六十进制-Verilog is used to achieve progress and six band, and combined into six decimal