搜索资源列表
mc8051_core
- 一个用VHDL写的8051的内核,很方便集成到FPGA里.-a written VHDL 8051 kernel, is a convenient integrated into the FPGA Lane.
FIRFIR1
- 基于FPGA的FIR串行滤波器设计与实现，本文运用VHDL编写-FPGA-based FIR filter design and implementation of the serial, the paper prepared by the use of VHDL
8.4-ADC0809-
- 基于VHDL语言，实现对ADC0809简单控制,ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系 --统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。 -Based on VHDL ADC0809 simple control, ADC0809 no internal clock, an external clock signal of 10KHz ~ 1290Hz here by the Departm
laser-echo-measurement
- 基于FPGA激光回波测时 VHDL语言实现-FPGA-based VHDL language when laser echo measurement
my_32fp_mult
- 这是一个计算32位浮点数的除法器，ALTERA的FPGA可直接用，用VHDL语言写的，希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
FIFO
- FIFO读写操作，quartusII VHDL IP FPGA-FIFO VHDL IP FPGA
MY 80c51 IP
- verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)