verilog实现UART收发源码 内有testbench-the UART transceiver Source for verilog implementation With testbench

写出七到三化简表达式并用verilog实现，与传统全加做比较。（内含testbench）-Write seven to three simplification expression verilog achieve, compared with the traditional full. (Including testbench)

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat