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sp605_pcie_x1_gen1_canuse
- xilinx 评估板sp605的PCIe的verilog源程序,已经经过调试。-failed to translate
Xilinx_PCIe_BMD
- xilinx FPGA 开发 PCIe BMD DMA的verilog HDL源码-xilinx fpga pcie Gen 1/2 bus master device---PCIe DMA with verilog HDL
exp6_Uart
- xilinx FPGA的rs232 Verilog HDL程序-xilinx FPGA的rs232 Verilog HDL