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exp09_3
- 可编程定时器_计数器,调用控制8253计数器,可打印记数结果.-programmable timer counters, call control 8,253 counter, can print the results in mind.
TESTJSQ
- 专用于计数器的检测，可同时测80个，分时控制，整机电流小，20A开关电源即可。
counter_4_bit
- 非常有参考价值的 计数器 源代码，用到了许多的编写程序的技巧，可以借鉴
counter
- 基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真
timeclock
- 数字钟的verilog实现程序。包含各个模块。分别为顶层模块，小时计数器，分计数器，秒计数器等。-Digital clock verilog implementation process. With each module. Were top-level module, hours counter, minutes counter, second counter and so on.
ex2
- FPGA数码管显示,带自动计数器，开发板实例教程-The FPGA digital display with automatic counter, the development board tutorial examples
COUNT0
- 用VHDL语言编写的一种24位的计数器，带即时锁存功能，带清零、控制功能。已经经过仿真验证。-A 24 bit counter with the VHDL language, with instant latch function, with clear, control function. Has been verified through simulation.
jsq
- 一个计数器的编程，是基于51内核的，很完整的实例程序-A counter programming is based on 51 core, it is full of examples of procedures
sjnd
- EDA的29进制计数器，采用quartus完成，学校实验经常用-EDA s 29 binary counter, using quartus complete, the school often experiment
数字跑表VHDL
- 基于VHDL 实现1小时的数字跑表，包含计数器、数据存储等部分(VHDL realization of digital stopwatch based on 1 hours, including counter, data storage etc.)