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XHDL4[1].0.40
- 实现VHDL和verilog之间的语言转换，方便程序之间的以致，XHDL版本4.0.40。-Achieved between VHDL and verilog language conversion between programs so easy, XHDL version 4.0.40.
key_interface
- verilog写的程序，是带按键消抖程序。。对于新手具有参考-verilog write the program, with key debounce program. . A reference for the novice
key_scan1
- 用verilog语言描述的键盘扫描程序，用于FPGA芯片以及矩阵键盘的测试。-With verilog language keypad scanning procedure.For the FPGA chip and matrix of the keyboard.
debounce
- 按键消抖程序，用Verilog硬件描述语言编写，实现了按键消抖动作-Buffeting eliminate key procedures, using Verilog hardware descr iption language, the realization of the keys for jitter elimination
timeclock
- 数字钟的verilog实现程序。包含各个模块。分别为顶层模块，小时计数器，分计数器，秒计数器等。-Digital clock verilog implementation process. With each module. Were top-level module, hours counter, minutes counter, second counter and so on.
LCD1602
- verilog 语言写的LCD1602程序-The verilog language written LCD1602 procedures. . .
SOS_Generator_module
- verilog 写的sos程序。。可以做做哦-verilog write sos program. . Doing oh
TX_UART_DEMO
- verilog写的串口发送程序。。波特率可以自行设计-verilog write serial transmission program. . The baud rate can design their own
VGA_Proj_Picture
- verilog 语言写的VGA程序 可以参考一下-VGA verilog language written programs can reference
Simplified-2-frequency-divider
- 用verilog语言编写的两个2分频小程序，通过了验证。-Two small written in Verilog language frequency divider applet, passes validation.