xilinx FPGA的CLB高效设计，对提升设计质量很有用-xilinx FPGA' s CLB efficient design, to enhance the quality of design is useful

本文又用C语言实现了标准的自适应算术编码，拿它与用FPGA实现的改进后的自适应算术编码的仿真结果对比验证了这种改进后编码器编码的正确性。此种结构的编码效率很高，一个时钟编码一个数据比特，时钟频率可以达到50MHZ，占用的硬件资源大约有800个CLB(可配置逻辑模块)。-This thesis realizes the adaptive arithmetic coding which is not improved with C language，compare with the result o

Xilinx 7系列的详细介绍，包括CLB,MEMORY,时钟管理等，对理解7系列FPGA有很大帮助。-Xilinx 7 series of details, including the CLB, MEMORY, clock management, understanding the 7 series FPGA great help.

This document cab be used for development on 7 series FPGA.