搜索资源列表
FPGA_GPS_C_A
- 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。
c
- 这也是一个很不错的技术文档 关于FPGA
CRC_realization
- 详细介绍高效的CRC实现算法，多用在DSP或者FPGA这种效率要求很高的硬件上。编码环境是C-Details of the CRC algorithm efficient, multi-DSP or FPGA used in demanding that the efficiency of hardware. Coding environment is C
Digital Filter implementation by FPGA
- 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on
CPLD-radom
- 基于C P L D 的伪随机序列发生器，用FPGA产生随机序列的-CPLD-based pseudo-random sequence generator, generate random sequences using FPGA
DVB
- DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
c
- 一个不错的FPGA设计技巧总结，只要你有一定的FPGA基础，就能对你产生帮助-FPGA design skills a good summary, as long as you have a certain amount of FPGA-based, we can help you generate
TheRealizationofAdaptiveArithmeticCoderWithFPGA.ra
- 本文又用C语言实现了标准的自适应算术编码，拿它与用FPGA实现的改进后的自适应算术编码的仿真结果对比验证了这种改进后编码器编码的正确性。此种结构的编码效率很高，一个时钟编码一个数据比特，时钟频率可以达到50MHZ，占用的硬件资源大约有800个CLB(可配置逻辑模块)。-This thesis realizes the adaptive arithmetic coding which is not improved with C language，compare with the result o
sobel_filter
- implementation of SOBEL filter using FPGA board RC200 in handle-c
dspic_comm.c.tar
- program to test the communication between the DsPIC card and FPGA cart
Mini_Proj3
- Embedded 16 bit adder designed and implemented on Altera FPGA DE1 board using SOPC system builder and tested with NIO2 software. Language:Verilog and C
Practical-FPGA-Programming-in-C
- sopc buider and c system
CPCI_PCIbus
- 为构建一个紧凑、灵活的 CPC I系统,在 IP核的基础上,采用 FPGA来实现 PCI总线接口电路。-To construct a compact and flex ible CPC I syste m, the PCI i nte rface c i rcuit i s i mp l em ented by FPGA based on IP core。
fpga
- Mini-Curso em português Dispositivos reconfigur´ aveis s˜ ao dispositivos que podem ser programados para ter o comportamento de um circuito l´ ogico em hardware. Diferentemente de Circuitos Integrados de Aplica¸ c˜ ao Espec
wimax_LDPc
- 基于C++和FPGA的wimax LDPC 编译码器的设计，编码方法不同，但性能都很良好-Wimax LDPC codec based on C++ and FPGA design
RS
- 在CMMB,IEEE 802.16d及DVB标准中RS码编解码器的设计与实现，其算法及FPGA实现，RS编解码的C源代码程序-Design and implementation of RS encoding and decoding in CMMB, IEEE 802.16d, and the DVB standard algorithm and FPGA implementation, RS codec C source code program
pts_papr_simula_implemantation
- ABSTRACT In this paper, the design and implementation of OFDM system along with Multi-Point Square Mapping combined with PTS (M-PTS) technique has received much attention in reducing the high peak to average power ratio (PAPR) of Orthogonal Frequen
vivado HLS开发教程
- 官方文档，与vivado HLS开发相关，介绍了HLS的特点和作用，即如何通过高级语言如C生成硬件描述语言，并生成IP核，方便FPGA开发。并给出了一些具体例程。
fpga_ztj
- 对于FPGA状态机的设计心得 对于FPGA状态机的设计分为两类，分为mealy状态机和Moore状态机，mealy状态机的输出不仅与当前输入有关还与当前状态有关，而Moore状态机的输出仅与当前状态有关。对于状态机描述首先要知道输入，输出，当前状态，下一个状态的基本定义。 对不状态机的设计，首先要有一个初始状态，一般命名为IDLE，其状态一般设定在复位信号到来时。 对于时钟敏感的信号，在其最大的一个时钟周期作为总的状态循环，最下的一个时钟信号最为一个状态指令，一般用于时序图的描述；对
microblaze example
- 用FPGA的软核跑的小工程，用于参考～microblaze软核可运行c程序，嵌入式系统学习