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A New Phase-Locked Loop (PLL) System
- An enhanced phase-locked loop (PLL) system is presented and its properties and performance characteristics are investigated. Advantages of the proposed PLL structure over the conventional PLLs including its capability of direct estimation of ampli
A Nonlinear Adaptive Filter for Online Signal
- This paper presents various applications of a nonlinear adaptive notch filter which operates based on the concept of an enhanced phase-locked loop (PLL). Applications of the filter for online signal analysis for power systems protection, control a
dxz
- 低相噪、低杂波数字锁相环路滤波器的设计,caj格式，下载前请安装相应阅读器-Low phase noise, low-noise digital phase-locked loop filter design, caj format, download the pre-install the corresponding reader
COSTAS
- 根据韦瓦[ Weawa] 单边带调制解调法、COSTAS 锁相环及双线性变换, 提出基于软件无线电的单边带锁相解调器。解调器运行在TMS320C6203 上, 能实时处理160kHz 信号, 捕捉8kHz 频偏。-According to韦瓦[Weawa] SSB modulation and demodulation method, COSTAS PLL and the bilinear transform, based on software radio single sideband ph
suoxianghuan
- 在数据采集系统中，锁相环是一种非常有用的同步技术，因为通过锁相环，可以使得不同的数据采集板卡共享同一个采样时钟。-In the data acquisition system, the phase-locked loop is a very useful synchronization technology, because the adoption of phase-locked loop, you can make the different data acquisition boards
Phase_Locked_Loop
- Very good code for Phase locked Loop in matlab
PLL
- Practical Phase-Locked Loop Design.rar
simplex_wireless_calling_system
- 单工无线呼叫系统分发射和接收两大部分。发射部分采用锁相环式频率合成器技术， MC145152和MC12022芯片组成锁相环，将载波频率精确锁定在35MHz，输出载波的稳定度达到4×10-5，准确度达到3×10-5，由变容二极管V149和集成压控振荡器芯片MC1648实现对载波的调频调制；末级功放选用三极管2SC1970，使其工作在丙类放大状态，提高了放大器的效率，输出功率达到设计要求。接收部分以超大规模AM/FM立体声收音集成芯片CXA1238S为主体，灵敏度、镜像抑制、信噪比等各项性能指标均达
2009
- 智能全数字锁相环的设计,基于FPGA实现。-Intelligent all-digital phase-locked loop design, FPGA-based implementation.
PLL_1
- Block model of a phase locked loop implemented in Simulink. Step 1 of a series of 5 developed models.
PLL2
- Block model of a phase locked loop implemented in Simulink. Step 2 of a series of 5 developed models.
PLL3
- Block model of a phase locked loop implemented in Simulink. Step 3 of a series of 5 developed models.
time_model_PLL
- Block model of a phase locked loop implemented in Simulink. Step 4 of a series of 5 developed models.
time_model_PLL1
- Block model of a phase locked loop implemented in Simulink. Step 5 of a series of 5 developed models.
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
digital_pll
- 传统的数字锁相环系统是希望通过采用具有低通特性的环路滤波器，获得稳定的振荡控制数据由于数字电子技术的迅速发展，尤其是数字计算和信号处理技术在多媒体、自动化、仪器仪表、通讯等领域的广泛应用，用数字电路处理模拟信号的情况日益普遍。所以模拟信号数字化是信息技术的发展趋势，而数字锁相环在其中扮演着重要角色。-Conventional digital PLL system is to have a low-pass characteristics by using the loop filter to o
Response-of-a-First-Order-Phase-Locked-Loop-to-Tw
- Response of a First-Order Phase Locked Loop to Two Sinusoidal Inputs
three-phase-phase-locked-loop-(-PLL-)
- three phase pll 5 harmunic
The-principle-of-phase-locked-loop
- 主要介绍了锁相环的基本原理，PLL参数测试示例展示，重点分析了CD4046——通用的CMOS锁相环集成电路，MT8870——音调译码器(Tone Decoder)是MITEL 公司所开发生产为一颗常用复频译码IC。-Introduces the basic principles of phase-locked loop, PLL parameter test sample shows, analyzes the CD4046-- generic CMOS PLL IC, MT8870-- ton
Phase-Locked-Loop-PLL-lecturer
- 锁相环实验，PLL参数测试，锁相环PLL原理与应用，环路滤波器 -The experimental phase-locked loop, PLL parameter testing, and application of the principle of the PLL loop filter