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EAUserGuide
- 視覺化的塑模工具,Enterprise Architect這套工具，有支援圖形轉換成10種以上的程式語言(Actionscr ipt、Ada、C and C++、C#、Java、Delphi、Verilog、PHP、VHDL、Python、System、C、VB.Net、Visual Basic)與DDL(SQL scr ipt)-Visual modeling tool, Enterprise Architect set of tools, support for graphics into
VHDL中有关进程及时间周期问题及解答
- 1. Analyze and simulate the following code lists (code1 and code 2) with the same input signals shown below by presenting POW and OL. If the data type of “a, b, c, d, u, v, w, x, y, z” is declared as std_logic, what changes the simulation outputs wil
Digital Filter implementation by FPGA
- 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on
DVB
- DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
TheRealizationofAdaptiveArithmeticCoderWithFPGA.ra
- 本文又用C语言实现了标准的自适应算术编码，拿它与用FPGA实现的改进后的自适应算术编码的仿真结果对比验证了这种改进后编码器编码的正确性。此种结构的编码效率很高，一个时钟编码一个数据比特，时钟频率可以达到50MHZ，占用的硬件资源大约有800个CLB(可配置逻辑模块)。-This thesis realizes the adaptive arithmetic coding which is not improved with C language，compare with the result o
renyiboxing
- 信号发生器是一种常用的仪器，能够实现各种波形，不同频率的输出，电子测试系统的重要部件。本研究 的数字信号发生器足基于直接数字合成即DDS技术设计的，采用VHDL与C语言相结合的方法，通过查找存储 于ROM查找表中的各种标准波形数据，产牛频率Hf调并且高精度的正弦波、方波、锯齿波等常用信号，并且町 以通过修改表中的数据，实现任意信号发生器-Signal generator is a commonly used instrument to achieve a variety of wav
chuzuche
- 一款基于VHDL的EDA计程车计费系统的设计.熟悉Quartus2操作环境-LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY liuxuanyi IS PORT(C:IN STD_LOGIC_VECTOR(2 DOWNTO 0) DP: OUT STD_LOGIC A1,A2,A3,B1,B2,B3:IN STD_LOGI
dasdaaa
- 、、： 请选择 Visual C++ Visual Basic DOS Unix_Linux C++ Builder Java Windows_Unix Delphi C-C++ PHP-PERL PHP Perl Python HTML Asm Pascal Borland C++ Others MultiPlatform C++ VFP SQL PDF TEXT WORD VBscr ipt Javascr ipt ASP CSharp CHM FlashMX matlab PowerBui
doxygen_manual-1.8.3
- Doxygen是一种开源跨平台的，以类似JavaDoc风格描述的文档系统，完全支持C、C++、Java、Objective-C和IDL语言，部分支持PHP、C#。注释的语法与Qt-Doc、KDoc和JavaDoc兼容。Doxgen可以从一套归档源文件开始，生成HTML格式的在线类浏览器，或离线的LATEX、RTF参考手册。-a code document generator tool for * C/C++ * Java * Objective-C * Python * ID
Digital-Logic-And-Microprocessor-Design-With-VHDL
- tài liệ u này mình up lên các bạ n tham khả o nhan, nế u có sai sót mong mọ i ngư ờ i góp y
12
- 在vhdl语言的环境下，自己设计正弦信号发生器，其中也包含一小段c语言程序-In vhdl language environment of their own design sinusoidal signal generator, which also contains a small c language program
fli_c_vhdl_cosimulation
- using modelsim foreign language interface for c-vhdl cosimulation and for simulator control on linux x86
CVHDL
- 从指令层面，比较了以C为代表的高级语言和VHDL语言的特点，适合初学者理解VHDL语言和高级语言的区别-Compared the difference between C code and VHDL code
NLmeansfilter
- my name ahmed nagieb, i worke in university of scince and technology in sudan ilearn some about matlab and c , c++, labview , vhdl
VHDL-Cookbook
- VHDL-Cookbook是一本讲解VHDL的书籍-The VHDL Cookbook First Edition The purpose of this booklet is to give you a quick introduction to VHDL. This is done by informally describing the facilities provided by the language, and using examples to illustra
max31855开发资料
- MAX31855热电偶转换器开发流程 一、 准备硬件和相关知识 1. 硬件：一块开发板、逻辑分析仪、热电偶（常用的K型热电偶）、杜邦线等； 2. 相关知识： VHDL基础、SPI通信； 二、 max31855datasheet编程用到的部分： 1．电路连接图 2．串行接口时序特性 3 .串口时序 4.引脚分配 5.热电偶温度格式 三、程序编写 /** *****