搜索资源列表
apb.rar
- APB master verilog code,APB master verilog code
advice-for-VHDLVerilog
- 对于VHDL、Verilog的可综合的代码风格的介绍和对初学者的建议-For VHDL, Verilog code that can be integrated style of presentation and suggestions for beginners
cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
iic_master
- it is a iic source verilog code with its testcase which can act only as master
Verilog编码与综合中的非阻塞性赋值CummingsSNUG2000S
- Verilog编码与综合中的非阻塞性赋值-Verilog code and synthesis must blocking evaluation
uart
- UART schematic and code
i2c_verilog
- verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
xapp460
- xilinx hdmi tx rx verilog code datasheet
verilog_circuits
- describes the verilog code for logic circuits
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
Stepper_controller_MAx
- stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog qu
source_code
- verilog code fifo memory usb
FIR
- FIR filter using verilog code
verilog-d-filp-flop
- Verilog code of D-Flip Flop
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
135--verilog-code-examples
- verilog设计实例，135个简单入门级代码示例-verilog design example, 135 simple entry-level code examples
Verilog-Code-For-Digital-Clock-Project
- Verilog code for digital clock project
Verilog-HDL-Code-Examples
- various verilog code ezamples for brginners.good point to start with.
ss_drive
- keyboard verilog code for nexys2 fpga borad
at7_ex02
- 8个拨码开关分别控制8个LED的亮灭状态。基于vivado平台编写的Verilog代码(8 dial switches control 8 LED's bright and dead state respectively. Verilog code based on vivado platform)