The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif

UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive