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- A Pipelined Implementation of AES for Altera FPGA platforms.doc
aes_pipe_latest.tar
- VERILOG IMPLEMENTATION OF PIPELINED AES ALGORITHM
ASE
- 可重构平台下AES算法的流水线性能优化，讲解比较到位，抛砖引玉可以-Reconfigurable platform performance optimization of pipelined AES algorithm, to explain more in place, so you can