高速数字传输技术, 时钟提取，均衡，高速采样 -high speed serdes， clock and data recovery, equalization, high-speed sampling

高速数字传输技术, 时钟提取，决策反馈均衡，高速采样, -high speed serdes， clock and data recovery, decision feedback-equalization, high-speed sampling

一种全数字时钟数据恢复电路的设计与实现，提出一种改进型超前滞后锁相环法的全数字时钟恢复算法，与同类电路比较，具有数据码率捕获范围宽、捕获时间短的优点。-Clock Date Recovery(CDR)circuit is a important part of data transmission equipment．For the burst data transmission，the traditional phase—lock loop can hardly achieve the re

12．5 Gb／s半速率时钟数据恢复电路(CDR)的 设计及6．25Gb／s SerDes接收芯片的系统集成，设计工艺均为TSMC 0．189in CMOS工艺。-aspects：Design of Half-rate 1 2．5 Gb／s Clock Data Recovery (CDR)and Integration of 6．25Gb／s SerDes receiver．Both are realized in TSMC 0．1 89m CMOS process．