搜索资源列表
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AccelDSP Synthesis Tool
Floating-Point to Fixed-Point
Conversion of MATLAB
Algorithms Targeting FPGAs
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本书编制的实验项目包括“CCS基本操作”、“基本算术运算”、“定点DSP的小数运算和浮点运算”、“DSP混合编程及CCS进阶”四个验证性实验和“数字正弦振荡器的DSP实现”、“FIR数字滤波器的DSP实现”两个综合性实验，并在综合性实验中配备了相关的设计性思考题供学有余力者进行全开放式实验。-Experimental projects include the preparation of the book " CCS basic operation" , " basic
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定點DSP的浮點開平方算法.pdf in TI C6000 DSP-Fixed-point DSP floating-point square root algorithm. Pdf in TI C6000 DSP
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ti公司TMS320C28X系列的IQMATH库为C/C++程序员收集了高度优化和准确的数学函数库并精确的在TMS320C28X芯片上将浮点算法
转换成固定点的运算代码，此文件为汉化版，为英文不好的技术人员提供了便利-ti company TMS320C28x series IQMATH library for C/C++ programmers to collect highly optimized and accurate mathematical function library an
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定点数只能表示一定范围内的数（整数或小数，有符号或者无符号），浮点数虽将表示数的范围给予了较充分的扩宽，但仍只能表示（理论上）无限精度的数；本导论将引入一种新类型的数——效数，来完美地表示数的范围和精度两个方面，并简要介绍（演示）效数的四则运算。-Fixed-point can only say that within a certain range of numbers (integer or decimal, signed or unsigned), floating point, said
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此文档是本人在用DM642跑8点FFT时做的测试工作，包含浮点和定点程序之间的效率对比。-This document is my DM642 running 8:00 in use when doing FFT testing, including procedures for floating point and fixed-point comparison between the efficiency.
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TI最新单片高性能DSP内核，内核以高性能TIC64X+体系架构为主体，结合浮点运算指令，频率达到1GHZ，同时支持定点和浮点运算-TI latest single high-performance DSP cores, high-performance TIC64X+ core architecture as the main body, combined floating-point instructions, frequency reached 1GHZ, supports fixed p
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High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational architecture—
two 32-bit IEEE floating-point
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本示例程序演示了如何计算定点和浮点各个长度和位数的按时间抽取FFT算法。所有程序在VC6下编译通过。-This sample application demonstrates how to calculate the various fixed and floating-point and the median length of time taken by FFT algorithm. All procedures under VC6 compile.
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介绍DSP中定点数与浮点数的表示形式，比如定点数的Q格式，定点数以及浮点数的运算-Introduced in DSP fixed point and floating-point representation, such as fixed-point Q-format, fixed-point and floating-point operations
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基于FPGA的单精度浮点数乘法器设计，本文设计了一个基于FPGA的单精度浮点数乘法器。乘法器为五级流水线结构。设计中采用了改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构，减少了部分积的数目，缩短了部分积累加的耗时；提出了对尾数定点乘法运算中Wallace树产生的2个伪和采用部分相加的处理方式，有效地提高了的运算速度；并且加入了对特殊值的处理模块，完善了乘法器的功能。单精度浮点数乘法器在Altera DE2开发板上进行了验证，其在Cyclone II EP2C35F672C6器
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A simple guide to Converting floating point to 32-bit fixed point in Java
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51单片机的定点和浮点运算子程序以及特殊功能寄存器和汇编指令的详细列表-51 single-chip fixed-point and floating-point operations subroutine, and a detailed list of the special function registers and assembly instructions
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To design fixed point to floating point encoder and experiment with
simulation, synthesis and implementation features of the Xilinx Project navigator.
Specifically, the objectives of this lab are:
1. To try out basic building blocks of VHDL beh
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1. 设计一个 N = 10 的低通 fir 滤波器，对 fs = 8kHz 的信号 fc = 2.5kHz
2. 设计等同性能的 IIR 滤波器
3. 定点实现，不能使用浮点
4. 测试多正弦波合成文件 MultiToneTest.wav 分析输出结果
5. 测试语音文件 sc03.wav 得到输出结果-1. Design a lowpass fir filter N = 10, for fs = fc 8kHz signal design equivalent of = 2.
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主要是DSP嵌入式开发的基础定点运算和浮点运算的讲解。-DSP embedded development mainly to explain the basis of fixed-point and floating-point arithmetic operations.
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一个关于matlab实现的定点仿真程序，FPGA之前的浮点转定点内容-On a fixed-point simulation program matlab implementation, FPGA floating-point turn before the designated content
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FLoating point / fix point basics
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