搜索资源列表
-
0下载：
用做定理证明、推理。可以扩展，比如与Z specification结合使用，做后期的verification。这个软件是软件工程学中formal method的一个很好的代表。-Isabelle is a generic proof assistant. It allows mathematical formulas to be expressed in a formal language and provides tools for proving those formulas in a lo
-
-
0下载：
Formal analaysis and verification of an OFDM modem design
-
-
0下载：
Symbolic logic generally supports the reasoning with propositions, i.e., with statements to be evaluated to true or false. Temporal logic is a special branch of symbolic logic focusing on propositions whose truth values depend on time.
-
-
0下载：
Formal verification of analog and mixed signal designs A survey
-
-
0下载：
formal verification -> verification hardware
-
-
0下载：
The Verilog
¤
Hardware Descr iption Language (HDL) is defined in this standard. Verilog
HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because
it is both machine readable and human readable, it
-
