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111
- 使用JK触发器设计111序列检测器，当检测到输入为111时输出为1，否则为0-JK flip-flop design using the sequence detector 111, when input 111 is detected when the output 1, otherwise 0
Jkflipflop
- it s a vhdl code for jk flip flop in vhdl
JK_FlipFlop
- Code for JK Flip-Flop
report_HW5_SoC_10052013
- JK flip-flop and traffic light in SystemC language
VHDL_trigger
- 本实验是VHDL的触发器实现，将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成在一个CPLD芯片中模拟其功能，并研究其相互转化的方法。-This experiment is the trigger of VHDL realize, will be basically RS flip-flop, synchronous RS flip-flop, the integrated JK flip-flop, D flip-flops simultaneously integrate
MIMASUO
- 用以74LS112双JK触发器构成的数字逻辑电路控制方案设计的数字密码锁有详细设计过程及源码。-To 74 ls112 double JK flip-flop consisting of digital logic circuit control the combination lock has a detailed design process of the scheme design and source code.
Exp-10-D-and-JK-FF
- D & JK FLIP FLOP USING MATLAB SOFTWARE