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High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational architecture—
two 32-bit IEEE floating-point
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精密工作台的光栅位移测量和控制系统 精密工作台的光栅定位测量和控制系统的设计 介绍了 国内外现状和光栅检测的历史。当今采用的原理和总体方案，放大整形、5倍频电阻链细分并联4细分辨向电路，24位可逆计数器
-Grating displacement precision stage control system for precision measurements and positioning table of the raster measurement, and control syste
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一种并行的有限域乘法器结构，用于ECC系统构建，多项式基-A parallel Finite Field Multiplier Architecture for ECC system construction, polynomial basis
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介绍用于光纤通信的速率为2.5 Gb/s的高速RS(255,239)译码器设计。对输入信号中可能出现的超
出译码器纠错能力的误码可进行检测判断,保证了误码不扩散。对译码器中大量使用的有限域乘法器进行了优化设计,尤其对并行钱氏搜索电路中的乘法器采用了按组优化设计方法,与直接实现方法相比,复杂度降低了45 -For optical fiber is introduced at a rate of 2.5 Gb/s (255239) of the high speed RS decoder des
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We present the design of a planar-integrated optoelectronic vector-matrix multiplier. The inherent
parallel-processing potential is fully exploited by optical implementation of multiplications and
summations. Planar integration makes the free-spa
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