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大量verilog代码
- 大量verilog设计实例
true_dual_port_ram_dual_clock
- 双端口ram的verilog程序，经过验证，可编译可用,-dual pot ram
Verilog-to-do-SD-card
- 本文档内是基于Verilog HDL的SD卡SPI模式下的读写程序，内有详细的注释，且通俗易懂。-This document is based on Verilog HDL in the SD card in SPI mode to read and write procedures, which are detailed notes, and easy to understand.
Verilog
- 是摩托罗拉关于Verilog HDL的开发规范，相信对于学习Verilog程序设计的人会有很大的帮助-Motorola on the development of Verilog HDL specification, I believe that learning Verilog for programming will be of great help to people
Code
- DSP学习板上的例子程序包括 AD转换 CAN总线 SPI SCI -Examples of on-board DSP learning process includes the AD conversion CAN Bus SPI SCI
MPEG2_TS_flow_embeded_control_data_design
- MPEG2_TS_flow_embeded_control_data_design.doc格式的有verilog程序！-MPEG2_TS_flow_embeded_control_data_design.docformat verilog program inside！
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
lcd1602verilog
- verilog lcd液晶1602驱动 这个程序的显示字符显示的是ASCII码，显示的数据由DB8输出到LCD上-verilog
crc_explain
- 循环冗余校验 CRC 的算法分析和程序实现。通信的目的是要把信息及时可靠地传送给对方，因此要求一个通信系统传输消息必须可靠与快速，在数字通信系统中可靠与快速往往是一对矛盾。为了解决可靠性，通信系统都采用了差错控制。本文详细介绍了循环冗余校验CRC（Cyclic Redundancy Check）的差错控制原理及其算法实现-Cyclic Redundancy Check
HuaWeiVerilog
- 主要用来介绍如何编写高质量的verilog程序的-Is mainly used to describes how to write high-quality verilog programs
clz
- 对于一串二进制数前置零的计数的Verilog程序-For a string of binary zero count Verilog pre-procedure
8254Verilog
- 用Verilog语言编写程序，基于FPGA实现设计8254的相关电子文件-With the Verilog programming language, based on FPGA to achieve the relevant electronic document design 8254
verilog
- verilog程序实例，各种简单程序，实用于多数初学者-verilog examples of procedures that a variety of simple procedures, practical for most beginners
16bit-Mulitiplier-Verilog-procedure
- 这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器-This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier
21-bit--leading-adder-Verilog
- 这是一个21位超前进位加法器的verilog程序。-21 bit leading adder verilog program.
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
16-leading-adder-Verilog-program
- 这是一个16位超前进位加法器的Verilog程序。-This is a 16 bit leading adder verilog program.
How-to-leanr-verilog
- Verilog 程序的学习，Verilog是通信工程专业学生经常使用的一种仿真程序-Verilog program of study, Verilog is a simulation program communication engineering students often use
Verilog的135个经典设计实例
- Verilog的135个经典设计实例，Verilog从业者学习者的很实用的资料(Classic design examples based on Verilog)
verilog分享--verilog快速掌握之模块例化
- 快速掌握verilog实例化分享程序，对于使用verilog编写的固件，需要功能划分，体现实例化的用处，便于归档提取，以备再次使用(Quickly grasp the Verilog instantiation sharing program, for the use of Verilog firmware, the need for functional division, to reflect the usefulness of instantiation, easy to archive