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Work_with_Modelsim_SE_and_Quartus_II
- 仔细讲解了如何在Modelsim中建立Altera的仿真库(Verilog HDL)，如何使用Modelsim建立工程以及代码调试中的注意事项。-Carefully explained how to create Altera simulation Modelsim library, how to use Modelsim to establish engineering and debugging the code in the note.
verilog-coding-rules
- Verilog HDL可综合RTL级代码设计规范及风格-Verilog HDL RTL level code design specifications and style
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
MOTOROLA-Verilog-HDL-Coding-standard
- 文档是关于verilogHDL的代码规范的，编写方是MOTOROLA，对于规范VerilogHDL格式有借鉴意义-Document is about verilogHDL code specification, the preparation side is MOTOROLA, VerilogHDL format for standardizing reference
Verilog-HDL
- 给出了学习verilog心得，其中包含了典型的代码例子，适合初学入门。-verilog program demo and method.
Verilog--exzampie
- Verilog的大量代码，拿去好好学习吧-verilog hdl exzamples
VGA全驱动
- 里面有关于FPGA设计的VGA的相应实验说明，以及相关代码