搜索资源列表
Designing_a_Multicycle_Processor--en
- 介绍怎样利用VHDL语言来实现一个多周期的处理器核心-on how to use VHDL to achieve more than one processor core cycle
FPGA_common
- 关于FPGA的一些常识及含IP核的VHDL设计源代码。-on FPGA with some common sense and VHDL IP core design of the source code.
567
- The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accur
encog-core-1.1.0
- VHDL制作的ann的code，希望大家可以用来作为参考-VHDL produced ann of the code, hope that can be used as a reference
TopLevel_DualPort_Ram_XilinxCore
- Top Level Dual Port Ram Core Project, VHDL code
TheResearchAndIPDesignOfSMBusBasedSmartBattery
- 本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。-This paper studies the SMBus specification, based on the introduction of the typical system
FreeDCT-L
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct-thesis
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct2
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
Robotic_Exploration_and_Landmark_Determination_us
- Sensing and planning are at the core of robot motion. Traditionally, mobile robots have been used for performing various tasks with a general-purpose processor on-board. This book grew out of our research enquiry into alternate architectures fo
avr_core2
- avr core porocesssor vhdl source code
AVR_Core
- another avr core porocesssor vhdl source code
C8051_mega_core.ZIP
- 8051 mega core porocesssor vhdl source code
m8051.tar
- another 8051 core porocesssor vhdl source code
ZX
- 本系统以51单片机及FPGA为控制核心，由正弦信号发生模块、功率放大模块、调幅（AM）、调频（FM）模块、数字键控（ASK，PSK）模块以及测试信号发生模块组成-The system of 51 single-chip and FPGA for the control of the core module by the sinusoidal signal, power amplifier module, AM (AM), frequency modulation (FM) module, dig
acceldsp1
- this the documentation of accel dsp software for dsp matlab to vhdl core
d
- IP核应用，详细的介绍了关于FPGA中IP核的应用-IP core application, a detailed presentation on the application of FPGA in the IP core ,,,,,,
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
Copy-of-VHDL-implementation-of-an-optimized-8-poi
- The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input datais a vector of 16 complex values