搜索资源列表
IIC-CPLD
- iic总线协议～IIC总线通讯接口器件的CPLD实现，网上下载的资料～～很不错-IIC bus protocol ~ IIC bus communication interface device CPLD realization of downloading the information ~ ~ very good
TLC549
- TLC548和TLC549是以8位开关电容逐次逼近A/D转换器为基础而构造的CMOS A/D转换器。它们设 计成能通过3态数据输出和模拟输入与微处理器或外围设备串行接口。TLC548和TLC549仅用输入/输出时 钟（I/O CLOCK） 和芯片选择（CS） 输入作数据控制。TLC548的最高I/O CLOCK输入频率为2.048MHz， 而TLC549的I/O CLOCK输入频率最高可达1.1MHz。 有关与大多数通用微处理器接口的详细资料已由工厂 准备好，可供使用。-TLC5
VHDLshiyan
- VHDL初学使用，希望大家能相互学习，共同进步！-The use of VHDL beginner, I hope that we can learn from each other, seek common progress!
led_zfsj
- 现场可编程门阵列( FPGA) 是一种可编程逻辑器件, 它具有丰富的I/O 口及内部资源, 编程和修改极为方便, 并且易于扩展和维护, 简化电子电路的设计。本系统采用Altera 公司的FLEX10K作为核心器件, 结合VHDL程序, 实现了对LED 点阵显示字符的控制。-Field programmable gate array (FPGA) is a programmable logic device, which has a wealth of I/O port and internal
vhdlexample
- vhdl初级学习者非常适合!!我相信这些资料会有很大的帮助的-vhdl very suitable for primary learners!! I believe that such information would be a great help! !
multifreqvhdl
- 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。-According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe tha
ps2files
- Project descr iption for a VHDL mouse ps2 interface for the spartan 3 e board. do not take this into consideration because it s null i just only want to activate my account
Assignment-3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx I
VHDL-PROGRAM-FOR-IF-AND-NESTED-IF
- VHDL PROGRAM FOR IF AND NESTED IF here i enclosed if and nested if
dianliuyuanMSP430
- 基于MSP430系列单片机的直流电流源，quartus软件vhdl编程仿真的，里面含程序 并附有实物图，我呕心沥血之作-Based on MSP430 MCU DC current source, quartus software VHDL programming simulation, which contains the program together with the physical map, I worked hard to make
Digital-Logic-And-Microprocessor-Design-With-VHDL
- tài liệ u này mình up lên các bạ n tham khả o nhan, nế u có sai sót mong mọ i ngư ờ i góp y
VHDL
- Mọ i ngư ờ i tham khả o tài liệ u
run
- 利用vhdl 寫出讓CPLD 跑馬燈的型式 內容為:I love U-Marquee CPLD using vhdl write to the type content: I love U
shu-ma-guan
- 这是一个在七段数码管上显示时，分，秒的vhdl 完整程序，希望对大家有用。-This is a seven-segment digital tube display hours, minutes, and seconds vhdl complete program, I hope useful.
vhd2vl
- vhdl to verilog rtl converter, it support simple vhdl syntax, i think it is very useful
VHDL_IUST_Fall2012_90611046
- carry ripple adder and 7segment with vhdl.i hopr people who use this project di not just cheat it
Booth Multiplier
- I have uploaded the introduction of the booth multiplier project in VHDL code. IF anyone interested on this code give me a shout and i will upload the whole code in here.
mixed-language--desvription-of-a-4x4-comparator.z
- mixed language (i.e VHDL and verilog ) is used to compute 4x4 comparator.. vhdl full adder is imported to verilog main module.
CPU
- 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan
xilinx-idea-vhdl-master
- here I send VHDL code for IDEA algorithm