搜索资源列表
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Verilog_PPT
- 东南大学Verilog讲义 Verilog 语言作为CPLD和FPGA开发语言,比VHDL相比有更多的优势.-Southeast University Verilog notes Verilog language as CPLD and FPGA development language than VHDL have more advantages in comparison.
FPGAFIR
- FPGA-based high-order FIR filter design
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
FSM-design
- An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog-An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog
my_uart
- FPGA的串口程序,用verilog语言写的，没找到Verilog选项，放到VHDL里面了-USART in fpga
baheyxj
- 由（Verilog或VHDL）所完成的电路设计，可以经过简单的综合与布局，快速的烧录至 FPGA 上进行测试-By (Verilog or VHDL) to complete the circuit design, synthesis and layout, can be a simple rapid burning to test on the FPGA
Xilinx
- 使用Xilinx的FPGA开发教程，Xilinx平台主要支持VHDL和Verilog的编程和实现。-Using Xilinx FPGA development tutorial, Xilinx platform is mainly supported by the programming and implementation of VHDL and Verilog.