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VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
shuzizhongsheji
- 多功能数字钟设计 一、设计任务： （一）主体功能 用HDL设计一个多功能数字钟，包含以下主要功能： 1.计时及校时，时间可以24小时制或12小时制显示 2.日历：显示年月日星期，及设定设定功能 3.跑表：启动/停止/保持显示/清除 4.闹钟：设定闹钟时间，整点提示 -multifunctional design of a digital clock, design tasks : (1) the main function of HDL design with a
Verifying_the_Quality_of_Your_Testbench_with_code_
- Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore
pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
fre_ctrl
- 利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL descr iption of the behavior and structure of a descr iption of the realization of frequency
ABEL-HDL_Reference
- VHDL进行设计输入开发的工具，好东西，快下载-VHDL design input to develop a tool for good, fast download
HDL_Design_style
- 关于HDL硬件描述语言的设计风格的资料，很有使用价值。-HDL Hardware Descr iption Language on the design of the information, very useful.
FPGA-basedincrementalphotoelectricencodercountcirc
- 基于FPGA的增量式光电编码器计数电路设计,文章含有Verileg HDL代码.-FPGA-based incremental photoelectric encoder count circuit design, the article contains Verileg HDL code.
VerilogHDL_tuxiang
- 介绍一种用于卫星姿态测量的CMOS图像敏感器--STAR250的时序驱动信号，并使用Verilog HDL语言设计驱动时序电路。经布线、仿真、测试后验证了驱动信号的正确性。 -Introduce a measurement for the satellite attitude CMOS image sensor- STAR250 timing drive signals, and use the Verilog HDL language design-driven sequential circ
verilog
- A popular cookbook describing the Verilog language for the design of integrated circuits. Verilog is the alternative to VHDL and is the favoured HDL design language in the USA. It is easier (quicker) to learn than VHDL because it is not so tightly ty
fjq2
- CPLD 支持在系统可编程( ISP) 技术, ISP 技术是 通信专用集成电路设计的一种最新设计方法, 它使得数 字电路设计、生产和维护发生革命性的变化[1 ]。本文对 数字语音通信系统中的复接ö 分接器进行了详细的设计 分析, 并利用软件MAX+ PLU S II 和V erilog- HDL 语 言进行具体的仿真和设计。-CPLD supports in-system programmable (ISP) technology, ISP Communicatio
DouglasHDL
- Douglas Smith HDL Chip Design (OCRed)
verilog-traffic-light
- 基于VerilogHDL设计的交通灯控制系统本设计利用Verilog HDL 语言、采用层次化混合输入方式,可控制4个路口的红、黄、绿、左转四盏信号灯,让其按特定的规律进行变化。 -This design using Verilog HDL language, adopt hierarchical mixed input method, four intersection control of red, yellow, green, left four lamp lights, let its
Activation-Function-Design-HDL-Coder
- Activation function design
Principles-of-Verifiable-RTL-Design
- 本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中 Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面， 是目前进行IC设计的同仁们最为推荐的一本宝典-Book HDL (verilog/vhdl), a detailed account of the IC DESIGN FLOW, Verification and Test of design ideas, methods and techniques, and
High-speed-Digital-Design
- 高速数字设计，针对verilog HDL，中文版-High-speed digital design verilog HDL, the Chinese version
Advance-HDL-Design-Training-On-Xilinx-FPGA
- dvance HDL Design Training On XilinxFPGA thanhmaikmt dao thanh mai
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
Principles-of-Verifiable-RTL-Design
- 本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中 Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面， 是目前进行IC设计的同仁们最为推荐的一本宝典-(Kluwer) Principles of Verifiable RTL Design (2nd Ed.)
Advanced-Digital-Design-with-the-Verilog-HDL-1st-
- Advanced Digital Design with the Verilog HDL 1st Ed. solution manual by Ciletti