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dxz
- 低相噪、低杂波数字锁相环路滤波器的设计,caj格式，下载前请安装相应阅读器-Low phase noise, low-noise digital phase-locked loop filter design, caj format, download the pre-install the corresponding reader
COSTAS
- 根据韦瓦[ Weawa] 单边带调制解调法、COSTAS 锁相环及双线性变换, 提出基于软件无线电的单边带锁相解调器。解调器运行在TMS320C6203 上, 能实时处理160kHz 信号, 捕捉8kHz 频偏。-According to韦瓦[Weawa] SSB modulation and demodulation method, COSTAS PLL and the bilinear transform, based on software radio single sideband ph
simplex_wireless_calling_system
- 单工无线呼叫系统分发射和接收两大部分。发射部分采用锁相环式频率合成器技术， MC145152和MC12022芯片组成锁相环，将载波频率精确锁定在35MHz，输出载波的稳定度达到4×10-5，准确度达到3×10-5，由变容二极管V149和集成压控振荡器芯片MC1648实现对载波的调频调制；末级功放选用三极管2SC1970，使其工作在丙类放大状态，提高了放大器的效率，输出功率达到设计要求。接收部分以超大规模AM/FM立体声收音集成芯片CXA1238S为主体，灵敏度、镜像抑制、信噪比等各项性能指标均达
2009
- 智能全数字锁相环的设计,基于FPGA实现。-Intelligent all-digital phase-locked loop design, FPGA-based implementation.
PLL_1
- Block model of a phase locked loop implemented in Simulink. Step 1 of a series of 5 developed models.
PLL2
- Block model of a phase locked loop implemented in Simulink. Step 2 of a series of 5 developed models.
PLL3
- Block model of a phase locked loop implemented in Simulink. Step 3 of a series of 5 developed models.
time_model_PLL
- Block model of a phase locked loop implemented in Simulink. Step 4 of a series of 5 developed models.
time_model_PLL1
- Block model of a phase locked loop implemented in Simulink. Step 5 of a series of 5 developed models.
fjq1
- 介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接 对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳 定可靠, 设计是成功的。-Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic devic
ppl
- 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programm
vco15-10
- Phase locked loop fundamentals
AN177
- An overview of the phase locked loop
licenta-(Sescu-Alexandru-(5404)-)
- PHASE LOCKED LOOP DESIGN
CPandI
- pll仿真,锁相环的设计与simulink下的仿真图。准确的。-pll simulation, phase-locked loop design with simulink under the simulation diagram. Accurate.
DDS_Lock_In_Amplifier
- 采用锁相环,直接数据合成技术创建的工程,在FPGA实现-Using phase-locked loop, direct data integration technologies to create works in the FPGA
Carrier-Recovery
- 本论文详细了关于载波恢复的锁相环原理，可以借鉴下，讲的不错-Of this thesis in detail on the carrier recovery phase-locked loop principle, can learn from the next, talking about good
Matlab-about-pll
- 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全 数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable t
three-phase-phase-locked-loop-(-PLL-)
- three phase pll 5 harmunic
The-principle-of-phase-locked-loop
- 主要介绍了锁相环的基本原理，PLL参数测试示例展示，重点分析了CD4046——通用的CMOS锁相环集成电路，MT8870——音调译码器(Tone Decoder)是MITEL 公司所开发生产为一颗常用复频译码IC。-Introduces the basic principles of phase-locked loop, PLL parameter test sample shows, analyzes the CD4046-- generic CMOS PLL IC, MT8870-- ton