时序约束，可以优化FPGA的性能，是FPGA的高级应用-Timing constraints, you can optimize the performance of FPGA is a high-level application of FPGA

利用定时器实现定时采集在vb中，可利用定时器的interval属性设置每秒钟采集的次数，把采集段程序放在定时器的timer事件中来实现数据采集。对于一般计算机来讲，由于受系统硬件能力的限制，定时器每秒钟最多只能产生18个事件，若时间间隔设置得过小，将达不到预期效果　　应用实例下面给出数据采集软件程序中部分主要源代码-Timer timing acquisition in vb, can take advantage of the acquisition of the number of time

Synopsys® Timing Constraints and Optimization User Guide

Xilinx时序约束文档，包括什么情况下使用时序约束、为什么要时序约束、如何进行时序约束等。-Xilinx timing constraint document, including under what circumstances the use of timing constraints, why should the timing constraints, how to carry out the timing constraint.