搜索资源列表
I2C
- 一种IIC的vhdl实现，包含相关sourcecode和协议文档，学习verilog hdl的好资料。-A kind of IIC' s vhdl implementation, the agreement contains the relevant sourcecode and documentation, learning verilog hdl good information.
DirectX_Updater
- Do I HAVE to backannotate to use these models? No but, to ensure correct results, you must pass the correct values to the models s generics. This can be done by editing the model s instantiations in your netlist. SDF backannotation may be easier
liyamin_slides
- 基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用AHDL编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and user manual,
ddc
- 电子科大2009-应用于无线电监测的高速信号处理平台设计，软件无线电的DDC的FPGA实现！-UESTC 2009- applies to wireless monitoring of high-speed signal processing platform design, software radio DDC' s FPGA implementation!
CHU92A
- MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
AD
- ccd驱动程序的verilog语言描述，介绍了其中的一种方法-The CCD driver' s Verilog language to describe a
ADC_16bit.v
- 一个verilog编写的16位ADC程序。该程序方便了DAC的设计人员对DAC提供输入信号，以此可以获得理想的DAC所需信号-Verilog to write a 16-bit ADC program. The program facilitates the DAC' s designers to provide input signals to the DAC, in order to be able to get a good DAC desired signal
DDR2-controller
- My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another
DDR3-SDRAM-controller
- My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.
verilog-a-lrm-1-0
- The information contained in this draft manual represents the definition of the Verilog-A hardware descr iption language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranties whatsoever with respect t
SSI_read
- 使用Verilog 编程语言实现对11 bit 编码器SSI输出的读取(Use Verilog to read encoder,it's 11 bit and SSI output)