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cpld_fpga_SW
- 里面介绍了＂CPLD，FPGA软件编程＂，里面许多许多例子，还有原代码，我也是辛苦才收集到的资料，希望能给其他工程师派上用场．-they introduced the "CPLD, FPGA software program" Inside many, many examples, the original code, I also hard to collect the information in hopes of giving the other engineers u
Virtex.files
- 在FPGA系统设计中，要达到性能最大化需要平衡具有混合性能效率的元器件，包括逻辑构造(fabric)、片上存储器、DSP和I/O带宽。在本文中，我将向你解释怎样能在追求更高系统级性能的过程中受益于Xilinx® 的Virtex™ -5 FPGA构建模块，特别是新的ExpressFabric™ 技术。以针对逻辑和算术功能的量化预期性能改进为例，我将探究ExpressFabric架构的主要功能。基于实际客户设计的基准将说明Virtex-5ExpressFabric技术性能平
EP1C6_EP1C12
- Altera FPGA Cyclone I EP1C6 EP1C12 最小系统 开发板 -the minimum system of Altera FPGA EP1C6 and or EP1C12
FPGA
- 针对MT9M111数字图像传感器,采用Cyclone系列 EP1C6Q240C6作为主控芯片,设计并实现了ITU-R BT.656视频数据的采集、色彩空间转换、DVI-I显示控制的数字视频转换系统。系统可以将传感器的输入图像以1280×960(60Hz)和 1280×1024(60Hz)格式输出到DVI-I显示器上,并具有图像静止功能,同时在系统空闲时,可以将系统设置为待机状态,来降低功耗。-Aimed at the digital image sensor MT9M111,used Cyclo
moukuai
- 整理的一些FPGA模块资料，是用VERILOG语言写的，希望对大家有用。-Collate information on a number of FPGA module is used VERILOG language, and I hope useful for all of us.
F_P_G_A
- ths i s the document describing the fpga technology. gives the basic details about the fpga.
CPCI_PCIbus
- 为构建一个紧凑、灵活的 CPC I系统,在 IP核的基础上,采用 FPGA来实现 PCI总线接口电路。-To construct a compact and flex ible CPC I syste m, the PCI i nte rface c i rcuit i s i mp l em ented by FPGA based on IP core。
ad
- 程序是本人亲测，可实现fpga对ads804的高速数据采集，和输出。利用了fpga的fifo和ad芯片每六个时钟数据更新一次的原理-The program I pro-test, the FPGA the ads804 high-speed data acquisition and output. The principle of use fpga fifo and ad-chip is updated once every six clock data
FPGA-based-design-documentation
- 55篇基于FPGA的设计文档 希望对大家有用-55 I hope useful for FPGA-based design documentation
fpga-draw
- 二维图形加速器设计与实现。采用Verilog HDL语言对各功能模块进行了设计,包括画线、画圆、画椭圆、多边形填充以及区域复制等,总结了一套将算法使用硬件描述语言实现的一般流程.这是本人花了50大洋买的，吐血奉献-Design and implementation of a two-dimensional graphics accelerator. Using Verilog HDL language of each functional module design, draw lines, d
cRIO-base-configure
- 关于用CRIO开发FPGA的配置向导，希望对大家有用。-CRIO development on the use of FPGA configuration wizard, I hope useful.
PLL_100M
- 实现pll分频功能倍频功能可得到fpga说需要的频率实现多的时钟输入-Multiplier pll divide function to achieve functionality available fpga said I need to achieve multi-frequency clock input
Mojo Tut
- This is file include most of mojo tut. I hope it help everyone to learn how to program fpga. Thanks
_Binary-File-Reader
- I m Labview Programer Want send fpga samples for labview
Embedded-Hardware-Training.pdf
- 本书内容非常丰富，共分为3部分。第一部分：常用电路及元件。第二部分：PROTEL DXP.第三部分：FPGA/CPLD技术。-This book is very rich, is divided into three parts. Part I: Common circuits and components. The second part:. PROTEL DXP third part: FPGA/CPLD technology.
FPGA-IO-design
- FPGA I/O设计，从基础知识介绍到高速I/O设计案例。-FPGA I/O design, from the basics to introduce high-speed I/O design case.
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
Altera-FPGA-Testing-v1
- This document describes functionality testing of the Altera Cyclone III FPGA Starter Kit Development Board. It also includes testing of associated daughterboards, i.e. the ADA ADC/DAC board and the HSMC to GPIO adapter board.