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FPGA_GPS_C_A
- 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。
EAUserGuide
- 視覺化的塑模工具,Enterprise Architect這套工具，有支援圖形轉換成10種以上的程式語言(Actionscr ipt、Ada、C and C++、C#、Java、Delphi、Verilog、PHP、VHDL、Python、System、C、VB.Net、Visual Basic)與DDL(SQL scr ipt)-Visual modeling tool, Enterprise Architect set of tools, support for graphics into
sobel_filter
- implementation of SOBEL filter using FPGA board RC200 in handle-c
Mini_Proj3
- Embedded 16 bit adder designed and implemented on Altera FPGA DE1 board using SOPC system builder and tested with NIO2 software. Language:Verilog and C
AutoPilot_Coding_Style_C
- 这是关于AUTOPILOT 的编程风格的资料，autopilot可以自动将C语言转化为verilog代码，减少了verilog调试的麻烦，大大提高编程速度。-This is on AUTOPILOT the programming style information The autopilot will automatically C language into Verilog code, reducing the Verilog debugging trouble, greatly impro
systemverilog
- 是关于System Verilog的课件，简要介绍了了System Verilog的用法，主要介绍进行可仿真和可综合的硬件设计，作为Verilog的扩展，在抽象设计、测试平台和基于C语言的应用程序设计接口有重大改进。-About System Verilog courseware, brief introduction of System Verilog usage introduces conduct can be integrated simulation and hardware desi