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IIC-CPLD
- iic总线协议～IIC总线通讯接口器件的CPLD实现，网上下载的资料～～很不错-IIC bus protocol ~ IIC bus communication interface device CPLD realization of downloading the information ~ ~ very good
vhdlexample
- vhdl初级学习者非常适合!!我相信这些资料会有很大的帮助的-vhdl very suitable for primary learners!! I believe that such information would be a great help! !
multifreqvhdl
- 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。-According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe tha
ps2files
- Project descr iption for a VHDL mouse ps2 interface for the spartan 3 e board. do not take this into consideration because it s null i just only want to activate my account
Assignment-3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx I
VHDL-PROGRAM-FOR-IF-AND-NESTED-IF
- VHDL PROGRAM FOR IF AND NESTED IF here i enclosed if and nested if
vhd2vl
- vhdl to verilog rtl converter, it support simple vhdl syntax, i think it is very useful
VHDL_IUST_Fall2012_90611046
- carry ripple adder and 7segment with vhdl.i hopr people who use this project di not just cheat it
mixed-language--desvription-of-a-4x4-comparator.z
- mixed language (i.e VHDL and verilog ) is used to compute 4x4 comparator.. vhdl full adder is imported to verilog main module.
CPU
- 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan
texio-user-method
- T E X T I O 在V H D L 仿真与磁盘文件之间架起了桥梁，使用文本文件扩展V H D L 的仿真功能。本文介绍 TEXTIO 程序包，以一个加法器实例说明TEXTIO 的使用方法，最后使用ModelSim 对设计进行仿真， 并分析仿真结果。-TEXTIO between VHDL simulation and bridges the gap between the disk file, use a text file extension of VHDL simulation
sha256core_latest.tar
- Here I upload the VHDL code for SHA-256 encryption and decryption
twofish_latest.tar
- Here I upload the VHDL code for Twofish enc. and dec. algorithm
xilinx-idea-vhdl-master
- here I send VHDL code for IDEA algorithm
NLmeansfilter
- my name ahmed nagieb, i worke in university of scince and technology in sudan ilearn some about matlab and c , c++, labview , vhdl