简易数字钟的设计.doc

不错的数字钟设计教程，自己照着编写了一边，好使啊！-Good tutorial digital clock design their own written according to the side, so that ah!

CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des