用design compiler对verilog hdl的程序进行逻辑综合最后生成门级网表即用门生成的电路图。-Verilog hdl with design compiler of the logic synthesis procedure generates the final gate-level netlist that is generated with the door circuit.

Allegro design entry HDL training manual

完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。 -Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an

Advanced Digital Design with the Verilog HDL (M.D.Cilett)