搜索资源列表
用VHDL语言在CPLD_FPGA上实现浮点运算
- 用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD / FPGA achieve floating-point computation methods
tAtan2Cordic.rar
- 是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。,Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.
stx_cookbook.zip
- Altera公司高端FPGA高级综合指导手册，包括：算术运算单元，浮点处理技巧，数据编码格式转换，视频处理，仲裁逻辑，多路选择，存储逻辑，计数器，通信逻辑，循环冗余校验，随机和伪随机函数，加密和同步等编码风格和技巧；,advanced synthesis cookbook for Altera high-end FPGA(Stratix),incuding coding style and design tricks for arithmetic,floating points oper
vhdl.rar
- 该pdf 详细的介绍了 浮点小数的计算法则，和在vhdl程序中 浮点小数的表示方法，和乘除法的运用 希望对大家有用,The pdf in detail the calculation of the decimal floating-point rules, and procedures in vhdl decimal floating-point method, and the use of multiplication and division for all of us hope tha
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
sqrt
- 实现任意位数的开方算法，但是不是浮点的算法，-Square root algorithm for arbitrary digit, but not floating-point algorithm, thanks
pre_norm_sqrt
- 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
post_norm_addsub
- 浮点加减运算的后规格化VHDL程序源代码，很不错，希望对大家有用-Floating-point addition and subtraction operations after the standardized VHDL source code, it is good, I hope all of you a useful
VHDL
- VHDl在FPGA上实现浮点运算，给初学者使用-VHDL in FPGA to achieve floating-point operations for beginners
FLOAT
- 介绍关于FPGA的浮点加法器运算单元设计-Information on floating-point FPGA-adder cell design computing
floating-point-adder1
- 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
juzhenqufaqi
- 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
ADDER
- 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
在VHDL中实现高精度快速除法
- 高精度的浮点数除法运算，基于浮点运算的FPGA实现，单精度浮点数-High-precision floating-point division operation, the FPGA based on the realization of floating-point operations, single precision floating point
floating_point_adder
- 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
matlab
- 16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!
16bitfloatingFFT
- 给出了16位浮点FFT的算法代码及相关资料-Given a 16-bit floating-point FFT algorithm code and related information
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
Floating_Point
- 基于FPGA的浮点小实验 hdl 语言描述-float point based on FPGA
基于VHDL实现单精度浮点数的加-减法运算
- vhdl 加法器和减法器 希望对VHDL的同学有参考作用(VHDL adder and function as relative reference)