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ATmega64e
- 高性能、低功耗的8 位AVR® 微处理器 • 先进的RISC 结构，JTAG 接口( 与IEEE 1149.1 标准兼容)-high performance, low power AVR 8
1149
- poj 1149 pigs 最大流的例题 还要写什么-poj 1,149 pigs maximum flow of excellence he wrote.
JTAGrep
- OPEN-JTAG ARM JTAG 測試原理 1 前言 本篇報告主要介紹ARM JTAG測試的基本原理。基本的內容包括了TAP (TEST ACCESS PORT) 和BOUNDARY-SCAN ARCHITECTURE的介紹，在此基礎上，結合ARM7TDMI詳細介紹了的JTAG測試原理。 2 IEEE Standard 1149.1 - Test Access Port and Boundary-Scan Architecture 從IEEE的JTAG測試標準開始，JTA
1149.1
- jtag协议，IEE1149.1协议文档。
jtag-0.5.1
- JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter.
1149.1边界扫描资料
- 边界扫描的几篇好论文
jtag
- JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like b
IEEE_JTAG_Atmel_ATF1502BE
- The ATF1502BE device is an In-System Programming (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan Descr iption Language (BSDL).
jtag-0.6-cvs-20051228
- JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter
1149.4VHDL
- Norm 1149.1 implemented in VHDL language.
[DataBus].1149.1
- IEEE std 1149.1-2001总线相关资料，是英文的。-1149.1 bus-related information is in English.
IEEE-1149.1
- JTAG(Joint Test Action Group，联合测试行动小组)是1985年制定的检测PCB和IC芯片的一个标准，1990年被修改后成为IEEE的一个标准，即IEEE1149.1-1990。IEEE 1149.1标准就是由JTAG这个组织最初提出的，最终由IEEE批准并且标准化的。所以，这个IEEE 1149.1这个标准一般也俗称JTAG调试标准。
JTAG-interface-introduce
- JTAG(Joint Test Action Group；联合测试行动小组)是一种国际标准测试协议（IEEE 1149.1兼容），主要用于芯片内部测试。
jtag_VCPP_src
- VC++ 实现JTAG(1149.1)的烧写，JTAG测试单片机(arm,arv)源代码。-vc++ releasize jtag 1149.1 programmer test microchip(arm, avr )and so on.
jtag_slave.4
- 1.1 Compliant with IEEE 1149.1 1.2 Support mandatory BYPASS, SAMPLE/PRELOAD, EXTEST instructions 1.3 Support user register connection beetween TDI-TDO 1.4 Boundary-scan register consist of cell type BC_1
ARM JTAG Debug
- 这篇文章主要介绍 ARM JTAG 调试的基本原理。 基本的内容包括了 TAP (TEST ACCESS PORT) 和 BOUNDARY-SCAN ARCHITECTURE 的介绍， 在此基础上， 结合 ARM7TDMI 详细介绍了的 JTAG 调试原理。(OPEN-JTAG Development Group.)