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fpga时钟设计
- 无沦是用离散逻辑、可编程逻辑,还是用全定制硅器件实现的任何数字设计,为了成功地操 作,可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将 导致错误的行为,并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可 分为如下四种类型:全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上 述四种时钟类型的任意组合。-without the expense of discrete logic, programmable l
Model_and_simulate_discrete-event_systems
- SimEvents® extends Simulink® with tools for discrete-event simulation of the transactions between components in a system architecture. You can use the architecture model to analyze performance characteristics such as end-to-end latencies, t
Discrete-Manufacturing-Enterprise-Logistics-System
- 基于离散制造企业的物流系统设计Discrete Manufacturing Enterprise Logistics System-Discrete Manufacturing Enterprise Logistics System