搜索资源列表
rece_7E
- HDLC控制接收数据开始标志7E和去零模块，用于FPGA与E1相接，Verilog HDL语言编写
e1_vhdl
- 用VHDL在FPGA内部实现E1的接口，适合通讯相关专业硬件开发使用-Within the FPGA implementation using VHDL E1 interface, the hardware for communications-related professional development to use
ethtoe1
- 硕士论文 基于FPGA的Ethernet+over+E1接口芯片的设计与实现.pdf-master paper the design and implentation of Ethernet+over+E1
prj
- bitfiles for T1/E1 analis in fpga
34342342432
- 基于FPGA的PCIE1接口设计与实现.pdf-the design and implmentation of PCI and E1 interface based on FPGA.
V35interface-communicate
- V.35接口与E1接口之间转换的基本原理,介绍了E1信道分时隙通信的基本过程，叙述了基于FPGA用VHDL和QuartusII来仿真本系统设计与实现的过程。-V.35 interface and E1 interface to convert between the basic principles of E1 channel introduces the basic process of communication sub-time slot, described by VHDL and FP
bert
- 误码测试仪，基于FPGA的E1口误码测试仪-BER tester, based on FPGA-E1 port BER tester
e1framerdeframer
- E1成帧器和解帧器的FPGA实现源码，测试可用-E1 Framer deframer