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fm0
- 使用matlab生成fm0编码，下载到信号发生器输出。
UHF+RFID中曼彻斯特及fm0编解码解决方案
- 曼彻斯特及fm0编解码解决方案
fm0_encode
- 详细介绍了fm0编码，采用verilog编码语言-fm0 encoding, using verilog
iso18000
- 这是一篇超高频RFID的ISO18000协议的手持机读卡器的硕士论文，基于linux平台的，讲的很好！-This is a UHF RFID, ISO18000 protocol handheld reader master' s thesis, based on linux platform, speaking of the good!
fm0
- fm0 encoder and coder
RFIDreceiver
- 对RFID读写器接收模块的解调以及fm0解码进行了MATLAB仿真。首先我们对读写器接收到的信号进行仿真，里面附带着标签信息；其次对接收到的ASK信号进行相干解调；接着解调后的信号经过抽样判决，进行fm0解码。仿真结果可表明接收到的信号与发射的信号一致。-On the RFID reader receiver module fm0 decoding and demodulation and a MATLAB simulation. First of all we readers received
fm0
- fm0解码程序，基于6B协议的读写器，对接收指令的解码 -fm0 decoding
fm0
- 用matlab实现的fm0(双相间隔码编码）编码-Matlab implementation of the fm0 (two-phase interval coding) encoding
fm0
- 485的串口通信程序，已经调通，可以使用-485 console
UHF-RFID-Manchesterand-fm0-encode
- UHF+RFID中曼彻斯特及fm0编解码解决方案-The Manchester, UHF+RFID and fm0 encoding and decoding solutions
phase-locked-loop-implementation
- 在fm0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When fm0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL
decode
- 通信数据中fm0数据的解码接收，解码数据和输出同步时钟。Verilog HDL-fm0 decoding the received data in the communication data, the decoded data and outputs sync clock。Verilog HDL
manfm
- Manchesteer-fm0 coding using verilog
FULLY-REUSED-VLSI-ARCHITECTURE-OF-fm0
- FULLY REUSED VLSI ARCHITECTURE OF fm0/MANCHESTER ENCODING USING SOLS TECHNIQUE FOR DSRC APPLICATIONS
ASK+fm0
- fm0编码(fm0 encode)