搜索资源列表
FPGA-MCU
- 介绍如何用单片机配置FPGA，仅供参考，如有疑问请联系我。-how to use microcontroller FPGA configuration, for reference purposes only, if any questions, please contact me.
Example-b3-1
- ALTER FPGA/GPLD设计（初级篇）的源码，只是其中的一部分供大家参考，如果还有用到其他的，请联系我-ALTER FPGA/GPLD design (primary chapter) of the source, is only one part of it for public consultation, if there are other uses, please contact me
VGA_move
- 基于FPGA的控制显示器程序。通过VHDL编程，下载到FPGA实验箱上。-FPGA-based process control monitor. Through the VHDL program, downloaded to test me on the FPGA.
cf_fir_latest.tar
- It is a fir to implement in a FPGA. It s not desenvolved for me it is a good work of another person
TheResearchoftherealtimesignalprocessingofSARbased
- 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging ar
mux4x1
- mux 4x1 designed by me in fpga adv pro
cordic_new
- Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation.-Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t
Hua-wei-FPGA
- 华为FPGA设计全套，我导师做课题时候给我的。-Huawei complete FPGA design, when I do the subject mentor to me.
clock
- 一个简单的FPGA时钟，里面有PDF说明~-A simple clock sample. There exists a PDF statement files in it. If there exists any problem please contact me.
MD5Transform
- 本人设计的一个基于FPGA平台用verilogHDL设计的MD5加密，供FPGA学习者学习参考-a MD5 encoder designed by me.It s a learning code for FPGA learner
nios2_flowwater
- 经典的nios2小例程，学习nios入门的经典例程。有疑问可登陆http://hongqinfpga.taobao.com/联系我，本人专门研究fpga嵌入式，欢迎朋友们一起加入学习。-Classic the nios2 small routines, learning the nios entry classic routines. Questions can visit http://hongqinfpga.taobao.com/ contact me, I specialize in th
NAND_flash_verilog_vhdl
- 很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。- NAND Flash Controller Reference Design =============================================================================== File List 1.
Ekran
- It is an Arkanoid game that is written by me in VHDL language. ı t is possible to play it via an altera FPGA and a monitor.
uart_tx
- It is an UART interface that is written by me in VHDL to receive and send datas from/to FPGA.
1002-1175(2008)02-0238-06
- 基于FPGA的Gardner定时同步算法实现，大家可以参考一下。如果哪位想设计Gardner，可以与我联系。-Gardner FPGA-based timing synchronization algorithm, we can refer to. If any want to design Gardner, you can contact me.
easy_step_motor.vhd
- FPGA kit with step motor chdl source code made by me
TX_RX
- FPGA用verilog实现串口和电脑的字符串以及单字符精准无误通信，即通过电脑向FPGA发送任一长度数据，FPGA返回PC相同的数据。波特率为9600，本例程为了得到精准的波特率使用了50M时钟的3倍频，测试可用，如有不明的地方，可以给我留言-FPGA implementation using verilog string and the computer serial port and single-character accurate communication, 9600, FPGA u
ram_2
- 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
SOLUTION_FOURIRER OPTICS
- thi is the last airbender me so alone