搜索资源列表
FPGA控制AD程序,ADC,DAC转换接口
- FPGA控制AD程序,ADC,DAC转换接口.rar 有限状态机控制AD采样.rar,FPGA control AD procedure
RS232串口通信协议
- RS232串口通信协议，verilog实现，通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
基于FPGA的直接数字频率合成器（DDS）设计
- 基于FPGA的直接数字频率合成器（DDS）设计 （源程序）,FPGA-based direct digital synthesizer (DDS) design (source code)
AD.FPGA控制AD7321的模块
- FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档。,FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.
NandFlash-FPGA-controller(ECC)
- 该压缩包包括NAND FLASH（美光）的FPGA控制器的原理及VHDL源码，非常具有参考价值。-The archive includes NAND FLASH (Micron) the principle of the FPGA and VHDL source code control, very valuable reference.
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
FPGA-DM9000A
- FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A for Verilog realization of Ethernet data sent and received
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
FPGA-DDS
- 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
verilog
- 组成原理的大作业，写一个计算器，用verilog语言写的-The composition of the major principles of operation, write a calculator, using the language written in Verilog
AM
- FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
VHDL
- 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY
FPGA
- 基于 FPGA 的运动目标检测系统的研究与开发 希望有哪位朋友需要-FPGA-based Moving Target Detection System for a friend who would like to have necessary
FPGA-LCD1602
- 基于FPGA的LCD1602显示，可根据实际内容修改显示内容-FPGA-based LCD1602 display can be modified according to the actual contents of display content
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
Verilog-hdlFPGA
- 关于FPGA的提高篇，Verilog HDL语言写的， 包含LCD控制VHDL程序与仿真，AD/DA，MASK，FSK，PSK，正弦波发生器，等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and VHDL simulation, AD/DA, MASK, FSK, PSK, sine wave generator, and so the classi
The Complete Verilog Book (Vivek Sagdeo)
- programming book verilog
FPGA研发牛人心得总结
- fpga 总结相关，建议看一看，希望有帮助(fpga relative,verilog,vhdl)
test_sd8_ychdj1280000
- fpga 开发，主要是针对nios核的一些开发，希望大家能相互的交流交流。(FPGA development, mainly for the development of some of the NIOS kernel, I hope we can exchange and exchange with each other)